Dynamic frequency scaling (also known as CPU throttling) is a technique in computer architecture that allows the frequency of a microprocessor to be adjusted. . Dynamic frequency scaling helps to reduce the cost of noise and reduce the cost of noise and overcompensation (eg after poor overclocking). Dynamic frequency scaling is used in all ranges of computing systems, ranging from mobile systems to data centers to reduce the power of the times of low workload.

The dynamic power (switching power) dissipated per unit of time by a chip is C · V 2 · A · f, where C is the capacitance being switched per clock cycle, V is voltage, A is the Activity Factor indicating the average number of switching events under the transistors in the chip (as a unitless quantity) and f is the switching frequency. Voltage is therefore the determinant of power usage and heating. The voltage required for steady operation is determined by the frequency at which the circuit is clocked, and can be reduced if the frequency is also reduced. Dynamic power alone does not account for the total power of the chip, however, as it is also static power, which is primarily because of various leakage currents. Convex energy behavior, ie, there is an optimal frequency of energy consumption, which is minimal. Leakage has become more important and more important. A decade ago, dynamic power accounted for about two-thirds of the total chip power. The power loss due to leakage currents in contemporary CPUs and SoCs tends to dominate the total power consumption. In the attempt to control the leakage power, high-k metal-gates and power gating have been common methods. Dynamic voltage scaling is another related technical conservation that is often used in conjunction with frequency scaling, as the frequency that is a chine may be related to the operating voltage. The efficiency of some electrical components, such as voltage regulators, increases with temperature. Since increasing the temperature, the CMOS formula indicates, and vice versa.

Dynamic frequency scaling reduces the number of instructions to a processor in a given amount of time, thus reducing performance. Hence, it is used when the workload is not CPU-bound. Dynamic frequency scaling by itself is rarely worthwhile as a way to conserve switching power. Saving the highest possible amount of power requires dynamic voltage scaling too, because of the V2 component and the fact that modern CPUs are highly optimized for low power idle states. In most constant-voltage cases, it is more efficient to run at peak speed and stay in a deep idle state for longer (called “race to idle” or computational sprinting), than it is to run at a reduced clock rate for a long time and only stay briefly in a light idle state. However, it can change those tradeoffs. A related-but-opposed technique is overclocking, whereby the processor’s performance is increased by ramping the processor’s (dynamic) frequency beyond the manufacturer’s design specifications. One major difference between the two is that in modern PC systems overclocking is mostly done on the front side of the bus (mainly because the multiplier is often locked), but dynamic frequency scaling is done with the multiply. Moreover, overclocking is often static, while dynamic frequency scaling is always dynamic. Software can often incorporate overclocked frequencies into the frequency scaling algorithm. One major difference between the two is that in modern PC systems overclocking is mostly done on the front side of the bus (mainly because the multiplier is often locked), but dynamic frequency scaling is done with the multiply. Moreover, overclocking is often static, while dynamic frequency scaling is always dynamic. Software can often incorporate overclocked frequencies into the frequency scaling algorithm. One major difference between the two is that in modern PC systems overclocking is mostly done on the front side of the bus (mainly because the multiplier is often locked), but dynamic frequency scaling is done with the multiply. Moreover, overclocking is often static, while dynamic frequency scaling is always dynamic. Software can often incorporate overclocked frequencies into the frequency scaling algorithm.

Intel’s CPU throttling technology, SpeedStep, is used in its mobile and desktop CPU lines. AMD employs two different CPU throttling technologies. AMD’s Cool’n’Quiet technology is used on its desktop and server processor lines. The aim of Cool’n’Quiet is not to save battery life, but it is not used in AMD’s mobile processor line, but instead with the purpose of producing heat, which in turn allows the system fan to spin down to slower speeds, resulting in cooler and quieter operation, hence the name of the technology. AMD’s PowerNow! CPU throttling technology is used in its mobile processor line, though some supporting CPUs like the AMD K6-2 + can be found in desktops as well. VIA Technologies used a LongHaul (PowerSaver) technology, while Transmeta’s version was called LongRun. The 36-processor AsAP 1 chip is one of the first multi-core processor chips to support completely unconstrained clock operation (including only those frequencies that are below the maximum allowed) including arbitrary changes in frequency, starts, and stops. The 167-processor AsAP 2 chip is the first multi-core processor chip that allows you to make your own clock. According to the ACPI Specs, the C0 working state of a modern-day CPU can be divided into the so-called “P” -states (performance states) which allow the clock rate reduction and “T” -states (throttling states) which will further throttle down a CPU (but not the actual clock rate) by inserting STPCLK (stop clock) signals and thus omitting duty cycles.